Tuesday, May 3, 2011
BittWare Anemone processor could make FPGAs as popular as general-purpose processors in embedded computing
Posted by John Keller.
One of the biggest raps against field-programmable gate arrays for digital signal processing is the complexity of the FPGA. To use these powerful-but-frustrating devices, systems designers must be adept in the arcane VHSIC Hardware Description Language (VHDL), as well as in hand-coding to achieve the most efficient performance. Using FPGAs is like a throwback to the old days of programming ASICs in assembly language to squeeze out the most performance possible.
As a result, many designers shy away from using FPGAs when they can, and opt instead for digital signal processing (DSP) architectures based on general-purpose processors like the 2nd Generation Intel Core i7 and on the new breed of graphics processing units (GPUs) like the NVIDIA CUDA. Using the GPP/GPU architecture for DSP-intensive floating-point processing, proponents argue, is easier and faster to market because the software can be written in high-order languages like C and C++, rather than the difficult VHDL.
Much of the reluctance to use FPGAs in DSP applications may be changing, however, with the introduction today of the FPGA/Anemone architecture from BittWare Inc. in Concord, N.H. Anemone is a floating-point co-processor that is programmable in the standard C computer language, which has the potential to make FPGA-based processors as easy and quick to use as the GPP/GPU architectures are becoming.
BittWare's new Anemone/FPGA architecture, which is based on Altera high-performance FPGAs and the Adapteva Epiphany processor, is designed for floating-point embedded computing applications like radar processing, software-defined radio, electronic warfare, and signals intelligence.
I think we'll be hearing a lot more about the Anemone/FPGA architecture in the future. ¶ 5/03/2011 07:24:00 AM
Posted by John Keller.
One of the biggest raps against field-programmable gate arrays for digital signal processing is the complexity of the FPGA. To use these powerful-but-frustrating devices, systems designers must be adept in the arcane VHSIC Hardware Description Language (VHDL), as well as in hand-coding to achieve the most efficient performance. Using FPGAs is like a throwback to the old days of programming ASICs in assembly language to squeeze out the most performance possible.
As a result, many designers shy away from using FPGAs when they can, and opt instead for digital signal processing (DSP) architectures based on general-purpose processors like the 2nd Generation Intel Core i7 and on the new breed of graphics processing units (GPUs) like the NVIDIA CUDA. Using the GPP/GPU architecture for DSP-intensive floating-point processing, proponents argue, is easier and faster to market because the software can be written in high-order languages like C and C++, rather than the difficult VHDL.
Much of the reluctance to use FPGAs in DSP applications may be changing, however, with the introduction today of the FPGA/Anemone architecture from BittWare Inc. in Concord, N.H. Anemone is a floating-point co-processor that is programmable in the standard C computer language, which has the potential to make FPGA-based processors as easy and quick to use as the GPP/GPU architectures are becoming.
BittWare's new Anemone/FPGA architecture, which is based on Altera high-performance FPGAs and the Adapteva Epiphany processor, is designed for floating-point embedded computing applications like radar processing, software-defined radio, electronic warfare, and signals intelligence.
I think we'll be hearing a lot more about the Anemone/FPGA architecture in the future. ¶ 5/03/2011 07:24:00 AM
